A long-recognized important objective in the constant advancement of monolithic IC (Integrated Circuit) technology is the scaling-down of IC dimensions. Such scaling-down of IC dimensions reduces area capacitance and is critical to obtaining higher speed performance of integrated circuits. Moreover, reducing the area of an IC die leads to higher yield in IC fabrication. Such advantages are a driving force to constantly scale down IC dimensions.
Referring to FIG. 1, a common component of a monolithic IC is a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) 100 which is fabricated within a semiconductor substrate 102. The scaled down MOSFET 100 having submicron or nanometer dimensions includes a drain extension implant 104 and a source extension implant 106 formed within an active device area 126 of the semiconductor substrate 102. The drain extension implant 104 and the source extension implant 106 are shallow junction implants to minimize short-channel effects in the MOSFET 100 having submicron or nanometer dimensions, as known to one of ordinary skill in the art of integrated circuit fabrication.
The MOSFET 100 further includes a drain contact junction 108 with a drain silicide 110 for providing contact to the drain of the MOSFET 100 and includes a source contact junction 112 with a source silicide 114 for providing contact to the source of the MOSFET 100. The drain contact junction 108 and the source contact junction 112 are fabricated as deeper junctions such that a relatively large size of the drain silicide 110 and the source silicide 114 respectively may be fabricated therein to provide low resistance contact to the drain and the source respectively of the MOSFET 100.
The MOSFET 100 further includes a gate dielectric 116 and a gate structure 118 which is typically a polysilicon gate. A gate silicide 120 is formed on the polysilicon gate 118 for providing contact to the polysilicon gate 118. The MOSFET 100 is electrically isolated from other integrated circuit devices within the semiconductor substrate 102 by shallow trench isolation structures 121. The shallow trench isolation structures 121 define an active device area 126, within the semiconductor substrate 102, where a MOSFET is fabricated therein.
The MOSFET 100 also includes a spacer 122 disposed on the sidewalls of the polysilicon gate 118 and the gate oxide 116. When the spacer 122 is comprised of silicon nitride (SiN), then a spacer liner oxide 124 is deposited as a buffer layer between the spacer 122 and the sidewalls of the polysilicon gate 118 and the gate oxide 116.
Referring to FIG. 1, dopants implanted into the drain contact junction 108 and the source contact junction 112, which are deeper junctions, and the gate structure 118 are activated typically using a RTA (Rapid Thermal Anneal) process at a relatively higher temperature such as at temperatures greater than 1000.degree. Celsius, for example, as known to one of ordinary skill in the art of integrated circuit fabrication. Such higher temperature activation in the deeper drain and source contact junctions 108 and 112 reduces silicide to contact junction resistance. In addition, such higher temperature activation in the gate structure 118 reduces poly-depletion effect within the gate structure 118 such that the speed performance of the MOSFET 100 is enhanced, as known to one of ordinary skill in the art of integrated circuit fabrication.
In contrast, the drain extension implant 104 and the source extension implant 106 are designed to be shallow junctions to minimize short-channel effects within the MOSFET 100, as known to one of ordinary skill in the art of integrated circuit fabrication. Thus, dopants within the drain extension implant 104 and the source extension implant 106 are activated typically using a RTA (Rapid Thermal Anneal) process at a relatively lower temperature such as at temperatures less than 1000.degree. Celsius, for example, as known to one of ordinary skill in the art of integrated circuit fabrication.
A fabrication process which uses such two separate RTA processes at two different temperatures is also known as a differential RTA (Rapid Thermal Anneal) process. During such a differential RTA process, activation of dopant with the RTA process using a relatively higher temperature is performed before activation of dopant with the RTA process using the relatively lower temperate. Thus, referring to FIG. 1, activation of dopant within the drain contact junction 108, the source contact junction 112, and the gate structure 118 with the RTA process using a relatively higher temperature is performed before activation of dopant within the drain extension implant 104 and the source extension implant 106 with the RTA process using a relatively lower temperature.
Referring to FIG. 1, during implantation of dopant into the drain contact junction 108, the source contact junction 112, and the gate structure 118, the spacer on the sidewalls of the gate structure 118 may be used for blocking the implantation of such dopant from the extension implant areas. Such a spacer is also known as a disposable spacer, as known to one of ordinary skill in the art of integrated circuit fabrication.
Referring to FIGS. 1 and 2, a conventional spacer 122 is comprised of silicon nitride (SiN). When such a spacer 122 including silicon nitride (SiN) is used on the sidewalls of the gate structure 118, the spacer liner oxide 124 is deposited as a buffer layer between the spacer 122 and the sidewalls of the polysilicon gate 118. Referring to FIG. 2, after the spacer 122 is used to block implantation of dopant from the extension implant areas 128, the spacer 122 is removed for implantation of dopant in the extension implant areas 128 for forming the drain extension implant 104 and the source extension implant 106. (Elements having the same reference number in FIGS. 1 and 2 refer to elements having similar structure and function.)
After the silicon nitride (SiN) spacer 122 is removed, the thin spacer liner oxide 124 remains. Because the spacer liner oxide 124 is relatively thin (typically in the range of 100 .ANG. (angstroms) to 200 .ANG. (angstroms) for example), the spacer liner oxide 124 may be difficult to etch off without adversely affecting the gate structure 118 which also has a small width of submicron or nanometer dimensions. However, implantation of dopant for forming the drain extension implant 104 and the source extension implant 106 while the thin spacer liner oxide 124 remains on the sidewalls of the gate structure 118 may result in insufficient overlap of the gate structure 118 over the drain extension implant 104 and the source extension implant 106. Such insufficient overlap results in large series resistance at the drain and the source of the MOSFET 100.
Referring to FIG. 3, a conventional silicon dioxide spacer 130 may be used for blocking implantation of dopant from the extension implant areas 128. Such a conventional silicon dioxide spacer 130 is formed by deposition of a layer of silicon dioxide over the whole surface of the semiconductor substrate 102 and then by patterning and etching the layer of silicon dioxide such that the silicon dioxide spacer 130 remains on the sidewalls of the gate structure 118. (Elements having the same reference number in FIGS. 1, 2, and 3 refer to elements having similar structure and function.)
However, with such formation of the conventional silicon dioxide spacer 130 of the prior art, a substantially triangular shape of the silicon dioxide spacer 130 results as illustrated in FIG. 3. Thus, the silicon dioxide spacer 130 has a substantially thinner width at the top away from the semiconductor substrate 102 and a thicker width at the bottom near the semiconductor substrate 102.
Referring to FIG. 3, after the spacer 130 is used to block implantation of dopant from the extension implant areas 128, the spacer 130 is removed for implantation of dopant in the extension implant areas 128 for forming the drain extension implant 104 and the source extension implant 106. However, with the substantially triangular shape of the silicon dioxide spacer 130 of the prior art, the top of the silicon dioxide spacer 130 having the thinner width would be etched off more quickly than the bottom of the silicon dioxide spacer 130 having the thicker width when a dry etch process is used. Unfortunately, the top of the gate structure 118 having scaled down submicron or nanometer dimensions may be significantly etched since the top of the silicon dioxide spacer 130 having the smaller width may be over-etched by the time the bottom of the silicon dioxide spacer 130 is sufficiently etched. On the other hand, if a wet etch were to be used for etching the conventional silicon dioxide spacer 130, then the thin gate dielectric 116 which typically is also comprised of silicon dioxide may undesirably be etched.
Because of these disadvantages of the spacers 122 and 130 of the prior art, an improved removable spacer is desired such that a differential RTA (Rapid Thermal Anneal) process may effectively be used for implantation and activation of dopant into the drain and source extension implants for scaled down MOSFETs having submicron or nanometer dimensions.